Method and apparatus for optimizing strobe to clock relationship
US7307900B2 · kind B2 · utility
5Cited by
3References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 30, 2004 |
| Grant date | Dec 11, 2007 |
| Priority date | — |
| Expiry date | Apr 25, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
To allow a memory controller to synchronize strobe to clock relationship for a DRAM, a register, such as, a flip flop, is incorporated within the DRAM to facilitate the sampling of SCLK with DQS. Likewise, while the DRAM is in a test mode of operation, the memory controller advances or retards the clock to DQS at the memory controller hub (MCH) to achieve the proper DRAM relationship. In one embodiment, the memory controller advances DQS if a binary zero value is read. In contrast, the memory controller retards DQS if a binary one value is read.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.