Joe Salmon
15Patents
5h-index
13Co-inventors
59Inventor score
Filing activity: Nov 23, 1999 → Jan 26, 2012
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6662305B1 | Fast re-synchronization of independent domain clocks after powerdown to enable fast system start-up | Electricity | 82 | Expired |
| US7459938B2 | Method and apparatus for power efficient and scalable memory interface | Emerging Cross-Sectional Technologies | 22 | Active |
| US7401246B2 | Nibble de-skew method, apparatus, and system | Physics | 12 | Active |
| US8495330B2 | Method and apparatus for interfacing with heterogeneous dual in-line memory modules | Physics | 6 | Active |
| US7447929B2 | Countering power resonance | Physics | 5 | Active |
| US7324403B2 | Latency normalization by balancing early and late clocks | Physics | 5 | Expired |
| US7307900B2 | Method and apparatus for optimizing strobe to clock relationship | Physics | 5 | Expired |
| US7555670B2 | Clocking architecture using a bidirectional clock port | Physics | 3 | Active |
| US7243176B2 | Method and apparatus for power efficient and scalable memory interface | Emerging Cross-Sectional Technologies | 3 | Expired |
| US8458507B2 | Bus frequency adjustment circuitry for use in a dynamic random access memory device | Physics | 2 | Active |
| US8468433B2 | Optimizing the size of memory devices used for error correction code storage | Physics | 1 | Active |
| US8108761B2 | Optimizing the size of memory devices used for error correction code storage | Physics | 1 | Active |
| US9237000B2 | Transceiver clock architecture with transmit PLL and receive slave delay lines | Electricity | 1 | Active |
| US7751274B2 | Extended synchronized clock | Electricity | 1 | Active |
| US7954001B2 | Nibble de-skew method, apparatus, and system | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.