Digital signal processor with cascaded SIMD organization
US7308559B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 7, 2003 |
| Grant date | Dec 11, 2007 |
| Priority date | — |
| Expiry date | Oct 18, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/8092
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A digital signal processor (DSP) includes dual SIMD units that are connected in cascade, and wherein results of a first SIMD stage of the cascade may be stored in a register file of a second SIMD stage in the cascade. Each SIMD stage contains its own resources for storing operands and intermediate results (e.g., its own register file), as well as for decoding the operations that may be executed in that stage. Within each stage, hardware resources are organized to operate in SIMD manner, so that independent SIMD operations can be executed simultaneously, one in each stage of the cascade. Intermediate operands and results flowing through the cascade are stored at the register files of the stages, and may be accessed from those register files. Data may also be brought from memory directly into the register files of the stages in the cascade.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.