PRAMs having a plurality of active regions located vertically in sequence and methods of forming the same
US7309885B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 7, 2005 |
| Grant date | Dec 18, 2007 |
| Priority date | — |
| Expiry date | Oct 27, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8828
Abstract
There are provided PRAMS having a plurality of active regions located vertically in sequence and methods of forming the same. The PRAM and the method provide an approach to rapidly changing phase in a phase change layer pattern with a given design rule. A semiconductor substrate defining at least one reference active region is prepared in a cell array region and a peripheral circuit region. Other semiconductor substrates on a vertical line passing a main surface of the reference active region are located in sequence. The other semiconductor substrates define other active regions, respectively. A lower cell gate pattern is formed on the semiconductor substrate of the reference active region, and upper cell gate patterns are disposed on the other semiconductor substrates of the other active regions, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.