Apparatus and methods for providing highly effective and area efficient decoupling capacitance in programmable logic devices
US7309906B1 · kind B1 · utility
7Cited by
8References
15Claims
0Family size
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Key dates
| Filing date | Apr 1, 2005 |
| Grant date | Dec 18, 2007 |
| Priority date | — |
| Expiry date | Dec 14, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/00
Abstract
Improved decoupling capacitor designs and layout schemes are provided that generate high effective capacitance and high area efficiency at higher frequencies than that of previously known decoupling capacitor designs. The improved decoupling capacitor designs utilize transistor gates with shorter channel lengths to reduce the total parasitic resistance of the channel, thereby providing higher effective capacitance at higher frequencies. To enable higher area efficiency of this decoupling capacitor design, excess contacts are replaced with polysilicon in a grid or waffle pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.