Method and stacked memory structure for implementing enhanced cooling of memory devices
US7309911B2 · kind B2 · utility
13Cited by
1References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 26, 2005 |
| Grant date | Dec 18, 2007 |
| Priority date | — |
| Expiry date | Dec 1, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1627
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method and structure are provided for implementing enhanced cooling of a plurality of memory devices. The memory structure includes a stack of platters. A sub-plurality of memory devices is mounted on each platter. At least one connector is provided with each platter for connecting to the sub-plurality of memory devices. A heat sink is associated with the stack of platters for cooling the plurality of memory devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.