Reducing the time to convert an analog input sample to a digital code in an analog to digital converter (ADC)
US7310058B2 · kind B2 · utility
3Cited by
8References
2Claims
0Family size
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Key dates
| Filing date | Jul 13, 2005 |
| Grant date | Dec 18, 2007 |
| Priority date | — |
| Expiry date | Jul 13, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/168
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A stage of a pipeline ADC which uses separate pairs of sampling network and amplifier (in a sample and hold circuit (SHA)) to provide inputs to quantizer (which generates a sub-code) and a switched capacitor network (implementing a DAC, a subtractor and amplification). Due to the use of separate components/paths to provide the input signal, the throughput performance of the ADC is enhanced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.