Method and apparatus for in-system redundant array repair on integrated circuits
US7310278B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 4, 2006 |
| Grant date | Dec 18, 2007 |
| Priority date | — |
| Expiry date | May 5, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/802
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a method of repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The method comprises the steps of providing the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The method comprises the further step of, at a given time, passing the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.