Across-thread out of order instruction dispatch in a multithreaded graphics processor
US7310722B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2003 |
| Grant date | Dec 18, 2007 |
| Priority date | — |
| Expiry date | May 28, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3888
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Instruction dispatch in a multithreaded microprocessor such as a graphics processor is not constrained by an order among the threads. Instructions are fetched into an instruction buffer that is configured to store an instruction from each of the threads. A dispatch circuit determines which instructions in the buffer are ready to execute and may issue any ready instruction for execution. An instruction from one thread may be issued prior to an instruction from another thread regardless of which instruction was fetched into the buffer first. Once an instruction from a particular thread has issued, the fetch circuit fills the available buffer location with the following instruction from that thread.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.