Method for correcting layout errors
US7310791B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 27, 2005 |
| Grant date | Dec 18, 2007 |
| Priority date | — |
| Expiry date | Dec 23, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for correcting layout errors of a layout, for example layout errors of a layout of an electronic circuit, is disclosed. In order to be able to correct such layout errors with the least possible complexity, the layout is examined for the presence of layout errors with the aid of predetermined design rules, identical layout errors are combined in a respective error class, and all layout errors of an error class that are still present are automatically corrected without further checking in an identical manner as soon as the correction of a layout error of the respective error class that is used as an error representative has been performed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.