Methods of fabricating semiconductor devices having thin film transistors
US7312110B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 4, 2005 |
| Grant date | Dec 25, 2007 |
| Priority date | — |
| Expiry date | Apr 4, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D88/00
Abstract
Methods of fabricating semiconductor devices are provided. An interlayer insulating layer is provided on a single crystalline semiconductor substrate. A single crystalline semiconductor plug is provided that extends through the interlayer insulating layer and a molding layer pattern is provided on the semiconductor substrate and the single crystalline semiconductor plug. The molding layer pattern defines an opening therein that at least partially exposes a portion of the single crystalline semiconductor plug. A single crystalline semiconductor epitaxial pattern is provided on the exposed portion of single crystalline semiconductor plug using a selective epitaxial growth technique that uses the exposed portion of the single crystalline semiconductor plug as a seed layer. A single crystalline semiconductor region is provided in the opening. The single crystalline semiconductor region includes at least a portion of the single crystalline semiconductor epitaxial pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.