Method of forming barrier metal in semiconductor device
US7312147B2 · kind B2 · utility
2Cited by
0References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 30, 2004 |
| Grant date | Dec 25, 2007 |
| Priority date | — |
| Expiry date | Jun 8, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76844
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a barrier metal in a semiconductor device. The present invention includes forming an insulating layer on a substrate having a lower metal line formed thereon, forming an opening exposing the lower metal line through the insulating layer, and forming a barrier metal layer on a sidewall of the opening and the insulating layer except the lower metal line by applying a positive voltage to the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.