Semiconductor device and fabrication method thereof
US7312531B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 28, 2005 |
| Grant date | Dec 25, 2007 |
| Priority date | — |
| Expiry date | Apr 11, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Semiconductor devices and methods for fabricating the same. The devices include a substrate, a catalyst layer, a second dielectric layer, and carbon nanotubes (CNTs). The substrate comprises an overlying first dielectric layer with an electrode embedded therein. The catalyst layer overlies the electrode and the first dielectric layer and substantially comprises Co and M1, wherein M1 is selected from a group consisting of W, P, B, Bi, Ni, and a combination thereof. The second dielectric layer overlies the catalyst layer and comprises an opening exposing parts of the catalyst layer. The carbon nanotubes (CNTs) are disposed on the exposed catalyst layer and electrically connect the electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.