Wafer level testing for RFID tags

US7312622B2 · kind B2 · utility

Assignee

• Impinj, Inc. · US

Inventors

• John D. Hyde · Corvallis, US
• Robert M. Glidden · Rancho Palos Verdes, US
• Andrew E. Horch · Sunnyvale, US
• Jay A. Kuhn · Seattle, US
• Ronald A. Oliver · Seattle, US

Key dates

• Filing date: Dec 15, 2004
• Grant date: Dec 25, 2007
• Expiry date: Jan 30, 2025

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/318511
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

Technologies suitable for on-wafer testing in the ubiquitous computing era are disclosed. Among the inventive features disclosed are: 1) clustering of wafer test probe landing area sites for parallel test sequencing; 2) on wafer test wiring that runs along the wafer's scribe regions; 3) on-wafer test wiring that can be scribed and yet thwart the spread of contamination into the product die; 4) an RFID tag design that allows for on-wafer testing without imposing substantial semiconductor surface area penalty; 5) an RFID tag design that includes built-in self test (BIST) circuitry for the RFID tag's non-volatile memory.