Method and apparatus for associating an error in a layout with a cell
US7313774B2 · kind B2 · utility
2Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 21, 2005 |
| Grant date | Dec 25, 2007 |
| Priority date | — |
| Expiry date | Feb 24, 2026 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P90/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
One embodiment of the present invention provides a system that associates an error in a layout with a cell. During operation, the system receives a layout which is designed to create a target feature with an intended shape. Next, the system determines an error in a critical dimension of the target feature. The system then identifies a cell in the layout based on the error's location in the layout, thereby associating the error with the cell. Note that associating errors with cells allows the errors to be summarized based on the associated cells, which can reduce the amount of time required to identify and fix the errors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.