Enhanced nitride layers for metal oxide semiconductors
US7314836B2 · kind B2 · utility
5Cited by
2References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2004 |
| Grant date | Jan 1, 2008 |
| Priority date | — |
| Expiry date | Dec 15, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/021
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The performance of NMOS and PMOS regions of integrated circuits is improved. Embodiments of the invention include forming a first dielectric layer optimized for n-doped regions over the n-doped regions and forming a second dielectric layer optimized for p-doped regions over p-doped regions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.