Technique to reduce ESD loading capacitance

US7315438B2 · kind B2 · utility

Assignee

• SEIKO EPSON CORPORATION · JP

Inventors

• Michael Hargrove · Clinton Corners, US
• Joseph Petrosky · Wappingers Falls, US

Key dates

• Filing date: Jun 10, 2003
• Grant date: Jan 1, 2008
• Expiry date: Mar 15, 2025

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D89/611

Abstract

The capacitive loading effects of an ESD circuit having an electrostatic-protection diode are reduced by using a capacitance compensation circuit. Under normal operation when no electrostatic discharge is experienced, the capacitance reduction circuit maintains a reverse bias across the electrostatic-protection diode, which causes the diode's capacitance to be reduced below a predetermined value. When an electrostatic discharged is experienced, the capacitance compensation circuit removes the applied reverse bias, and shunts the electrostatic-protection diode to a power rail.