Michael Hargrove
58Patents
13h-index
76Co-inventors
87Inventor score
Filing activity: Dec 23, 1993 → Jul 29, 2015
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US8048791B2 | Method of forming a semiconductor device | Electricity | 122 | Active |
| US6372559B1 | Method for self-aligned vertical double-gate MOSFET | Electricity | 78 | Expired |
| US6320225A | SOI CMOS body contact through gate, self-aligned to source- drain diffusions | Electricity | 59 | Expired |
| US6531375B1 | Method of forming a body contact using BOX modification | Electricity | 42 | Expired |
| US6433587B1 | SOI CMOS dynamic circuits having threshold voltage control | Electricity | 41 | Expired |
| US6335262B1 | Method for fabricating different gate oxide thicknesses within the same chip | Emerging Cross-Sectional Technologies | 32 | Expired |
| US9343300B1 | Methods of forming source/drain regions for a PMOS transistor device with a germanium-containing channel region | Electricity | 24 | Active |
| US5731941A | Electrostatic discharge suppression circuit employing trench capacitor | Electricity | 24 | Expired |
| US7932143B1 | Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methods | Electricity | 23 | Active |
| US9147730B2 | Methods of forming fins for FinFET semiconductor devices and selectively removing some of the fins by performing a cyclical fin cutting process | Electricity | 19 | Active |
| US6531741B1 | Dual buried oxide film SOI structure and method of manufacturing the same | Electricity | 17 | Expired |
| US8361894B1 | Methods of forming FinFET semiconductor devices with different fin heights | Electricity | 17 | Active |
| US9318342B2 | Methods of removing fins for finfet semiconductor devices | Electricity | 13 | Active |
| US5401130A | Internal circulation fluidized bed (ICFB) combustion system and method of operation thereof | Mechanical Engineering; Lighting; Heating | 13 | Expired |
| US7315438B2 | Technique to reduce ESD loading capacitance | Electricity | 12 | Expired |
| US8809178B2 | Methods of forming bulk FinFET devices with replacement gates so as to reduce punch through leakage currents | Electricity | 12 | Active |
| US6756637B2 | Method of controlling floating body effects in an asymmetrical SOI device | Electricity | 12 | Expired |
| US7723192B2 | Integrated circuit long and short channel metal gate devices and method of manufacture | Electricity | 12 | Active |
| US7598838B2 | Variable inductor technique | Electricity | 11 | Expired |
| US8076209B2 | Methods for fabricating MOS devices having highly stressed channels | Electricity | 11 | Active |
| US7767534B2 | Methods for fabricating MOS devices having highly stressed channels | Electricity | 11 | Active |
| US6344671B1 | Pair of FETs including a shared SOI body contact and the method of forming the FETs | Emerging Cross-Sectional Technologies | 10 | Expired |
| US7268645B2 | Integrated resonator structure and methods for its manufacture and use | Electricity | 10 | Expired |
| US8294211B2 | Semiconductor transistor device structure with back side gate contact plugs, and related manufacturing method | Electricity | 10 | Active |
| US7998832B2 | Semiconductor device with isolation trench liner, and related fabrication methods | Electricity | 9 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.