System and method for generating a jittered test signal
US7315574B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 26, 2005 |
| Grant date | Jan 1, 2008 |
| Priority date | — |
| Expiry date | Oct 25, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31917
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A multi-speed jittered signal generator (216, 400) that generates a full-speed jittered signal (404) by scaling a low-speed jittered signal (420) using a frequency scaler (428). The low-speed jittered signal is created by injecting a modulation signal (416) into a reference signal (412) using a jitter injector (432). Injecting jitter into a low-speed reference signal allows the full-speed jittered signal to be of higher quality than conventional jitter signals created by injecting jitter information into a full-speed reference signal. The multi-speed jittered signal generator may be used as part of a testing system (208) for testing various circuitry, such as high-speed serializer/deserializer circuitry (220).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.