Verification environment creation infrastructure for bus-based systems and modules
US7315803B1 · kind B1 · utility
2Cited by
4References
20Claims
0Family size
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Key dates
| Filing date | Feb 10, 2005 |
| Grant date | Jan 1, 2008 |
| Priority date | — |
| Expiry date | Feb 9, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318378
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method of building a verification environment within a software-based development tool for a programmable logic device can include determining an interface description for a bus functional model. The method further can include creating a hardware specification for the programmable logic device. The hardware specification can reference the bus functional model and at least one bus-based module interacting with the bus functional model. The verification environment for the programmable logic device can be automatically generated according to the interface description and the hardware specification.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.