Processor block placement relative to memory in a programmable logic device
US7315918B1 · kind B1 · utility
6Cited by
3References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 14, 2005 |
| Grant date | Jan 1, 2008 |
| Priority date | — |
| Expiry date | Mar 14, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/7857
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A programmable logic device having groups of data and instruction memory blocks separated by a processor block is described. The processor block including an embedded processor and data and instruction memory controllers. The data and instruction memory blocks respectively including data and memory groupings of block random access memories.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.