Chip dicing
US7316940B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 9, 2006 |
| Grant date | Jan 8, 2008 |
| Priority date | — |
| Expiry date | Aug 9, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/78
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor structure and method for chip dicing. The method includes (a) providing a semiconductor substrate and (b) forming first and second device regions in and at top of the substrate. The first and second device regions are separated by a semiconductor border region of the substrate. The method further includes (c) forming N interconnect layers, in turn, directly above the semiconductor border region and the first and second device regions. N is a positive integer greater than one. Each of the N interconnect layers includes an etchable portion directly above the semiconductor border region. The etchable portions of the N interconnect layers form a continuous etchable block directly above the semiconductor border region. The method further includes (d) removing the continuous etchable block by etching, and (e) cutting with a laser through the semiconductor border region via an empty space of the removed continuous etchable block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.