Method of fabricating a CMOS device with dual metal gate electrodes
US7316950B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 16, 2004 |
| Grant date | Jan 8, 2008 |
| Priority date | — |
| Expiry date | Dec 20, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of constructing a dual metal gate CMOS structure that uses an ultra thin aluminum nitride (AINx) buffer layer between the metal gate and gate dielectric during processing for preventing the gate dielectric from being exposed in the metal etching process. After the unwanted gate metal is etched away, the CMOS structure is annealed. During the annealing, the buffer layer is completely consumed through reaction with the metal gate and a new metal alloy is formed, resulting in only a minimal increase in the equivalent oxide thickness. The buffer layer and gate metals play a key role in determining the work functions of the metal/dielectric interface, since the work functions of the original gate metals are modified as a result of the annealing process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.