Semiconductor device having super junction structure and method for manufacturing the same
US7317213B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 26, 2005 |
| Grant date | Jan 8, 2008 |
| Priority date | — |
| Expiry date | Sep 28, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/127
Abstract
A semiconductor device includes: a center region; a periphery region; and a semiconductor layer including pairs of a first region having a first impurity amount and a second region having a second impurity amount. The first and the second regions are alternately aligned in a plane. The periphery region includes an utmost outer and an utmost inner periphery pairs. The utmost outer periphery pair has a difference between the second and the first impurity amounts, which is smaller than a maximum difference in the periphery region. The utmost inner periphery pair has a difference between the second and the first impurity amounts, which is larger than a difference in the center region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.