Optimization of NMOS drivers using self-ballasting ESD protection technique in fully silicided CMOS process

US7317228B2 · kind B2 · utility

Assignee

• LSI Logic Corporation · US

Inventor

• Jau-Wen Chen · Cupertino, US

Key dates

• Filing date: Feb 10, 2005
• Grant date: Jan 8, 2008
• Expiry date: May 17, 2025

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/0212

Abstract

Design and optimization of NMOS drivers using a self-ballasting ESD protection technique in a fully silicided CMOS process. Silicided NMOS fingers which include segmented drain diffusion. Specifically, the segmented drain diffusion provides self-ballasting resistors which improves the ESD performance. Preferably, the width of the each diffusion resistor is relatively small, as this can improve a non-uniform silicidation process. The resistance of the segmented diffusion resistors is determined by their width and length, and effectively increases the ballasting effect of parasitic n-p-n bipolar transistors.