Redundancy repair circuit and a redundancy repair method therefor
US7317645B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 29, 2005 |
| Grant date | Jan 8, 2008 |
| Priority date | — |
| Expiry date | Mar 29, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/802
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A redundancy repair circuit and method therefor for use with a semiconductor memory device are provided. The redundancy repair circuit comprises: a memory circuit having a plurality of address lines and a plurality of redundancy address lines in a memory cell; a repair redundancy control circuit for repairing a defective address line using a redundancy address line of the plurality of redundancy address lines, and for encoding and outputting fuse repair information corresponding to redundancy address information, wherein addresses corresponding to defective memory cells are pre-programmed; and a redundancy line driver for receiving the fuse repair information from the repair redundancy control circuit, for decoding the fuse repair information and for activating a redundancy line corresponding to the decoded fuse repair information, wherein the repair redundancy control circuit is separate from the redundancy line driver.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.