System and method for dynamic memory interleaving and de-interleaving
US7318114B1 · kind B1 · utility
23Cited by
5References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 29, 2004 |
| Grant date | Jan 8, 2008 |
| Priority date | — |
| Expiry date | Sep 29, 2025 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a system includes a plurality of memory controllers each coupled between a processor and a respective memory. Each memory controller includes a plurality of decoders. Each decoder of a given memory controller may be independently configurable to match on a respective value of a subset of address bits such as the low-order cache line address bits, for example, received in a memory request. In one specific implementation, the number of decoders included on a given memory controller may correspond to the number of ways in which the memory is interleaved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.