Address converter semiconductor device and semiconductor memory device having the same
US7319634B2 · kind B2 · utility
6Cited by
2References
33Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 8, 2006 |
| Grant date | Jan 15, 2008 |
| Priority date | — |
| Expiry date | Aug 8, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An address converter of a semiconductor device comprises a clock generating portion for generating at least one clock signal when a power voltage is applied; a control signal setting means for setting a control signal during a mode setting operation; a polarity selecting signal generating portion for generating at least one polarity selecting signal in response to the at least one clock signal and the control signal; and an address converting portion for converting at least one bit of an address applied from an external portion to output a converted address in response to the at least one polarity selecting signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.