System and method for analyzing electrical failure data
US7319935B2 · kind B2 · utility
2Cited by
38References
66Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 12, 2003 |
| Grant date | Jan 15, 2008 |
| Priority date | — |
| Expiry date | Sep 5, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2223/5442
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method to perform analysis on test results of multiple integrated circuits. Based on the analysis, the system and method display a wafer map having map indicators representing statistical values of the test results.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.