Method for on-chip signal integrity and noise verification using frequency dependent RLC extraction and modeling techniques
US7319946B2 · kind B2 · utility
3Cited by
9References
5Claims
0Family size
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Key dates
| Filing date | Oct 21, 2002 |
| Grant date | Jan 15, 2008 |
| Priority date | — |
| Expiry date | Nov 15, 2023 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/367
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
New Frequency dependent RLC extraction and modeling for on chip integrity and noise verification employs:
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.