Method for fabricating a transformer integrated with a semiconductor structure
US7321285B2 · kind B2 · utility
5Cited by
12References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 17, 2007 |
| Grant date | Jan 22, 2008 |
| Priority date | — |
| Expiry date | Apr 17, 2027 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49128
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A substrate is provided and a top interconnection metal layer and a primary winding layer are formed thereon. Then a passivation layer having a plurality of via exposed parts of the top interconnection metal layer is formed on the substrate. A secondary winding layer and at least a bonding pad are formed on the passivation layer. The bonding pad electrically connects to the top interconnection metal layer through the via.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.