Biasing structure for accessing semiconductor memory cell storage elements
US7321516B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 22, 2005 |
| Grant date | Jan 22, 2008 |
| Priority date | — |
| Expiry date | Apr 14, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A biasing structure for a memory cell storage element, for setting an operating voltage at an accession electrode of the memory cell storage element. The biasing structure includes a biasing transistor coupled to the accession electrode and adapted to set the operating voltage based on a biasing voltage received at a control electrode of the biasing transistor, and a biasing voltage generator for generating the biasing voltage. The biasing voltage generator includes a feedback voltage regulation structure adapted track changes in a threshold voltage of the biasing transistor, so as to keep the operating voltage at the accession electrode of the memory cell storage element substantially stable against operating condition changes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.