Method and apparatus for managing write-to-read turnarounds in an early read after write memory system
US7321950B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 3, 2005 |
| Grant date | Jan 22, 2008 |
| Priority date | — |
| Expiry date | May 22, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1647
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for managing write-to-read turnarounds in an early read after write memory system are presented. Memory controller logic identifies a write operation's bank set, allows a different bank set read operation to issue prior to the write operation's completion, and allows a same bank set read operation to issue once the write operation completes. The memory controller includes operation counter logic, operation selection logic, operation acceptance logic, command formatting logic, and memory interface logic. The operation counter logic receives new-operation-related signals from the operation acceptance logic and, in turn, provides signals to the operation selection logic and the operation acceptance logic as to when to issue a read operation that corresponds to either an even DRAM bank or an odd DRAM bank.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.