Method for testing flash memory power loss recovery
US7321951B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 17, 2003 |
| Grant date | Jan 22, 2008 |
| Priority date | — |
| Expiry date | Nov 28, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Non-volatile memory device, driver, and method is described that utilizes write or erase cycle tracking to interrupt or stop a non-volatile memory programming or erase operation at a selected point to interrupt/stop execution or simulate power loss at a specific point. This ability allows for a deterministic and repeatable testing process of all write or erase cycles of a non-volatile command where the state of floating gate memory cells are changed in the non-volatile memory device. Additionally, this ability to utilize write or erase cycle tracking to interrupt or stop a non-volatile memory programming operation or erasing operation at any selected point enables simulation of power loss at each point in a selected operation that a non-volatile floating gate memory cell is programmed or erased, allowing for improved, deterministic testing of the power loss recovery cycle and faster code/design change verification.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.