Method for software controllable dynamically lockable cache line replacement system
US7321954B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 11, 2004 |
| Grant date | Jan 22, 2008 |
| Priority date | — |
| Expiry date | Apr 23, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/125
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An LRU array and method for tracking the accessing of lines of an associative cache. The most recently accessed lines of the cache are identified in the table, and cache lines can be blocked from being replaced. The LRU array contains a data array having a row of data representing each line of the associative cache, having a common address portion. A first set of data for the cache line identifies the relative age of the cache line for each way with respect to every other way. A second set of data identifies whether a line of one of the ways is not to be replaced. For cache line replacement, the cache controller will select the least recently accessed line using contents of the LRU array, considering the value of the first set of data, as well as the value of the second set of data indicating whether or not a way is locked. Updates to the LRU occur after each pre-fetch or fetch of a line or when it replaces another line in the cache memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.