Integrated mechanism for suspension and deallocation of computational threads of execution in a processor
US7321965B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 27, 2004 |
| Grant date | Jan 22, 2008 |
| Priority date | — |
| Expiry date | Jun 6, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/54
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microprocessor includes a core configured to concurrently execute instructions of a plurality of program threads and a yield instruction, included in the instruction set of the microprocessor. The yield instruction includes an opcode for instructing the microprocessor core to suspend issuing instructions of a thread. The thread is one of the plurality of concurrently executed program threads. The yield instruction is an instruction in the thread. The yield instruction also includes a first operand. If the first operand is a first predetermined value the microprocessor core terminates issuing instructions of the thread. If the first operand is a second predetermined value the microprocessor core unconditionally reschedules issuing instructions of the thread. The yield instruction also includes a second operand for receiving a result value of the instruction usable by other instructions of the program thread.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.