Fabrication process for increased capacitance in an embedded DRAM memory

US7323379B2 · kind B2 · utility

Assignee

• MOSYS, INC. · US

Inventors

• Dennis Sinitsky · Baoshan, TW
• Fu-Chieh Hsu · Saratoga, US

Key dates

• Filing date: Feb 3, 2005
• Grant date: Jan 29, 2008
• Expiry date: Feb 3, 2025

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/37

Abstract

An embedded memory system includes an array of dynamic random access memory (DRAM) cells, which are isolated with deep trench isolation, and logic transistors, which are isolated with shallow trench isolation. Each DRAM cell includes an access transistor and a capacitor structure. The capacitor structure is fabricated by forming a metal-dielectric-semiconductor (MOS) capacitor in a deep trench isolation region. A cavity is formed in the deep trench isolation, thereby exposing a sidewall region of the substrate. The sidewall region is doped, thereby forming one electrode of the cell capacitor. A gate dielectric layer is formed over the exposed sidewall, and a polysilicon layer is deposited over the resulting structure, thereby filling the cavity. The polysilicon layer is patterned to form the gate electrode of the access transistor and a capacitor electrode, which extends over the sidewall region and upper surface of the substrate.