Method of fabricating semiconductor device
US7323419B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 25, 2006 |
| Grant date | Jan 29, 2008 |
| Priority date | — |
| Expiry date | Jan 25, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/32135
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a semiconductor device including a high-k dielectric for as a gate insulating layer is provided. The method includes forming a high-k dielectric layer and a conductive layer on a substrate, dry etching a portion of the conductive layer, performing a process to increase a wet etch rate of a remaining portion of the conductive layer, and forming a conductive layer pattern by wet etching the remaining portion of the conductive layer after performing the plasma process or the ion implantation. The process to increase the wet etch rate of the conductive layer including a plasma process and/or an ion implantation on the remaining portion of the conductive layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.