Fin field effect transistors having multi-layer fin patterns

US7323710B2 · kind B2 · utility

Assignee

• SAMSUNG ELECTRONICS CO., LTD. · KR

Inventors

• Young-Pil Kim · Eden Prairie, US
• Sun-Ghil Lee · Seojong-myeon, KR
• Si-Young Choi · Yongin-si, KR

Key dates

• Filing date: Jun 17, 2004
• Grant date: Jan 29, 2008
• Expiry date: Nov 10, 2025

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/6748

Abstract

A fin field effect transistor has a fin pattern protruding from a semiconductor substrate. The fin pattern includes first semiconductor patterns and second semiconductor patterns which are stacked. The first and second semiconductor patterns have lattice widths that are greater than a lattice width of the substrate in at least one direction. In addition, the first and second semiconductor patterns may be alternately stacked to increase the height of the fin pattern, such that one of the first and second patterns can reduce stress from the other of the first and second patterns. The first and second semiconductor patterns may be formed of strained silicon and silicon-germanium, where the silicon-germanium patterns can reduce stress from the strained silicon patterns. Therefore, both the number of carriers and the mobility of carriers in the transistor channel may be increased, improving performance of the fin field effect transistor. Related methods are also discussed.