Electrical interconnection structure formation
US7323780B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 10, 2005 |
| Grant date | Jan 29, 2008 |
| Priority date | — |
| Expiry date | Jun 21, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/04953
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An electrical interconnection structure and method for forming. The electrical structure comprises a substrate comprising electrically conductive pads and a first dielectric layer over the substrate and the electrically conductive pads. The first dielectric layer comprises vias. A metallic layer is formed over the first dielectric layer and within the vias. A second dielectric layer is formed over the metallic layer. A ball limiting metallization layer is formed within the vias. A photoresist layer is formed over a surface of the ball limiting metallization layer. A first solder ball is formed within a first opening in the photoresist layer and a second solder ball is formed within a second opening in the photoresist layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.