Automatic extension of clock gating technique to fine-grained power gating
US7323909B2 · kind B2 · utility
16Cited by
2References
20Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 29, 2005 |
| Grant date | Jan 29, 2008 |
| Priority date | — |
| Expiry date | Sep 8, 2025 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0016
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method extends a clock-gating technique to provide a sleep signal for controlling switch circuits that reduce active leakage power. Using this extension of the clock-gating technique, fine-grained power-gating is achieved. The method automatically identifies, at an RTL or a gate level, the logic circuits that can be power-gated. The method of the present invention derives a sleep signal for fine-grained power-gating that may be applicable to both time-critical and non-time-critical designs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.