Sense amplifier organization for twin cell memory devices
US7324396B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 20, 2005 |
| Grant date | Jan 29, 2008 |
| Priority date | — |
| Expiry date | Dec 27, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/4013
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device is provided that uses a single wordline to access both storage cells of a so-called twin cell. A memory device comprises a plurality of wordlines and a plurality of bitlines in an array, with a plurality of storage cells at certain intersections of wordlines and bitlines. A plurality of sense amplifiers are provided, each of which is connected to at least a first pair of bitlines to detect a voltage difference on the bitlines caused by the charge from a twin storage cell comprised of first and second storage cells at the intersection of a single wordline with said first pair of bitlines, respectively. As a result, each cell of a twin storage cell can be accessed with a single wordline.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.