Latency normalization by balancing early and late clocks
US7324403B2 · kind B2 · utility
5Cited by
12References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 24, 2004 |
| Grant date | Jan 29, 2008 |
| Priority date | — |
| Expiry date | Jan 18, 2025 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method, apparatus, and system are disclosed. In one embodiment the method comprises inputting an early clock signal and a late clock signal to a memory device and generating an average clock signal for the memory device by averaging the early clock signal and the late clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.