Techniques for reducing off-chip cache memory accesses
US7325101B1 · kind B1 · utility
9Cited by
7References
30Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 31, 2005 |
| Grant date | Jan 29, 2008 |
| Priority date | — |
| Expiry date | Apr 4, 2026 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0897
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Cache lines stored in an on-chip cache memory are associated with one or more state bits that indicate whether data stored in the cache lines was sourced from an off-chip cache memory or a main memory. By keeping track of the source of cache lines in the on-chip cache memory and by designing the replacement algorithm of the on-chip cache memory such that only one line in a given set maps into an off-cache memory cache line, the frequency of off-chip cache memory accesses may be greatly reduced, thereby improving performance and efficiency.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.