System and method for multiple cycle capture of chip state
US7325164B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 25, 2003 |
| Grant date | Jan 29, 2008 |
| Priority date | — |
| Expiry date | Oct 18, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318522
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Test circuitry is incorporated on a chip die together with a circuit to be tested, such as an ASIC or microprocessor, to provide external access to signals that are internal to an integrated circuit chip package. A controller provides the arm command and issues appropriate configuration controls to collect signal samples. In particular, a network responds to these commands from the controller to selectively provide signal samples from a device under test. A trigger event generator responds to logic or other characteristics of the signal samples to provide trigger events. These trigger events are counted by a trigger event counter in the armed state of the state machine to identify the final trigger event corresponding to an occurrence of a programmable number of the trigger events. A store event generator also responds to a programmed characteristic or combination(s) of the signal samples to provide a store event. Either or both of the event generators may use a mask to provide these events.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.