System and method to test integrated circuits on a wafer
US7325180B2 · kind B2 · utility
9Cited by
15References
58Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 26, 2003 |
| Grant date | Jan 29, 2008 |
| Priority date | — |
| Expiry date | Dec 10, 2024 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/303
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A system to test integrated circuits on a wafer may include a transceiver formed on the wafer. The system may also include an antenna system couplable to the transceiver. The transceiver may be formed in one of a scribe line on the wafer, a chip on the wafer or on an otherwise unusable portion of the wafer. The antenna system maybe formed in at least one of the same scribe line as the transceiver or in at least one other scribe line formed in the wafer. Alternatively, the antenna system may include an antenna external to the wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.