Electronic design for integrated circuits based process related variations
US7325206B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 17, 2002 |
| Grant date | Jan 29, 2008 |
| Priority date | — |
| Expiry date | Sep 30, 2023 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/3212
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An electronic design is generated for an integrated circuit that is to be fabricated in accordance with the electronic design by a process that will impart topographically induced feature dimension variations to the integrated circuit. The generating includes adjusting the electronic design based on predictions of topographical and topographical-related feature dimension variations by a pattern-dependent model. An RC extraction tool is used in conjunction with the generating and adjusting of the electronic design. The process includes a fabrication process that will impart topographical variation to the integrated circuit and a lithography or etch process. Placement attributes for elements of the integrated circuit are determined.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.