Patent · US Expired

Timing violation debugging inside place and route tool

US7325215B2 · kind B2 · utility

14Cited by

3References

19Claims

0Family size

Assignee

LSI Logic Corporation · US

Inventors

Matthias Dinter · Holzkirchen, DE
Juergen Dirks · Holzkirchen, DE
Herbert Johannes Preuthen · Dorfen, DE

Key dates

Filing date	Aug 31, 2005
Grant date	Jan 29, 2008
Priority date	—
Expiry date	Apr 5, 2026

Classification

Technology area (CPC G)Physics
CPC primaryG06F2119/12
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A method for developing a circuit design is disclosed. The method generally include the steps of (A) generating a violation display based on violation information provided from a place-and-route tool and (B) generating a layout display based on layout information provided from the place-and-route tool. The violation display may include (i) a plurality of performance violations for the circuit design and (ii) a plurality of user inputs each associated with one of the performance violations. The layout display may include a layout view of the circuit design. The layout view may highlight at least one of (i) a plurality of cells and (ii) a plurality of networks each along a path related to a particular one of the performance violations identified by a user through the user inputs.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.