Method of manufacturing MOS transistors with gate electrodes formed in a packet of metal layers deposited upon one another
US7326631B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 15, 2004 |
| Grant date | Feb 5, 2008 |
| Priority date | — |
| Expiry date | Jan 15, 2024 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Consistent with an example embodiment, a method of manufacturing a semiconductor device comprises MOS transistors having gate electrodes formed in a number of metal layers deposited upon one another. Active silicon regions having a layer of a gate dielectric and field-isolation regions insulating these regions from each other are formed in a silicon body. Then, a layer of a first metal is deposited in which locally, in a part of the active regions, nitrogen is introduced. On the layer of the first metal, a layer of a second metal is then deposited, after which the gate electrodes are etched in the metal layers. Before nitrogen is introduced into the first metal layer, an auxiliary layer of a third metal permeable to nitrogen is deposited an the first metal layer. Thus, the first metal layer can be nitrided locally without the risk of damaging the underlying gate dielectric.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.