Logic compatible non-volatile memory cell
US7326994B2 · kind B2 · utility
11Cited by
12References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 12, 2005 |
| Grant date | Feb 5, 2008 |
| Priority date | — |
| Expiry date | Mar 4, 2026 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
Abstract
A non-volatile memory cell and a method of manufacturing the same are provided. The non-volatile memory cell includes a semiconductor substrate, a floating gate over the semiconductor substrate, a first, a second, and a third capacitor each having a first plate and sharing a common floating gate as a second plate. The non-volatile memory cell further includes a transistor connected in series with the first capacitor. The gate electrode of the transistor is connected to a wordline of a memory array, and a source/drain region is connected to a bitline.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.